基于FPGA的高速数据采集及处理系统

High Speed Data Collection and Processing System based on FPGA

介绍了用FPGA逻辑控制多通道的模拟信号进行高速采样,并用FPGA对A/D转换的数据进行运算、存储和处理的方法,从而在减少CPU占用率(负担)的情况下实现了高速A/D及采样存储。该设计采用FPGA器件EP1C3T144C8N处理器,使用VHDL硬件语言进行编程;并在Quartus II平台下进行了软件编程和仿真验证。

An approach of using FPGA logic control multi-channel for high-speed sampling of the analog signal and using FPGA for the operations, storage and processing of the A/D conversion data is introduced to reduce the CPU usage and to realize high speed A/D, sampling and storage. The proposed design uses the FPGA device EP1C3T144C8N processor and the VHDL hardware language programming, and the whole design is programmed and simulated in the Quartus II platform.