0.13μm逻辑平台自对准工艺新型器件的优化

A New MOSFET Structure with Self-Aligned Polysilicon Source and Drain Electrodes on a 0.13 μm Logic Platform

增加一层多晶硅的自对准工艺已经被验证在0.5μm以上的逻辑工艺平台有效降低50%金属氧化物半导体场效应管的面积。然而随着栅极尺寸的不断缩小,自对准工艺的器件结构发生了变化,其器件的不均匀性效应越来越大地被凸现出来。文章以0.13μm的逻辑工艺为例,阐述了工艺中的器件不均匀性效应以及通过调整多晶硅的制程参数(温度)的方式予以解决的实例。

The self-aligned polysilicon approach with a second layer of polysilicon is demonstrated to decrease the effective MOSFET area comparing to the conventional device at the same design rule when the gate dimension is larger than 0.5 μm. When the channel length scales down the self-aligned technique encounters challenges on the existing MOS transistor structure. This paper presents the experimental study on the new MOSFET structure as well as the process fabrication procedure. The comparable device performance to the typical 0.13 μm logic technology is achieved with 50% MOSFET size smaller.