一种基于FPGA的全帧率图像处理方法

A Method of Processing Full-Frame Rate Image Based on FPGA

针对图像算法在FPGA内的硬件化实现问题,提出了一种全帧率处理的思路,并提供了两种具体的可供参考的设计方法——基于像素流缓冲的卷积核处理技术和基于相邻图像帧相关性的图像参数提取技术。通过其可以方便地设计并实现大部分空间域图像处理算法及其任意组合的硬件逻辑电路,并达到与图像输入帧率相同的处理速度。以Canny算子的硬件化实现为例验证了设计理念。实验结果表明,全帧率图像方法具有可操作性强、实时性好、符合结构化模块化设计的特点,特别适合于对实时性要求高的嵌入式视觉系统。

Focused on the hardware implementation of image processing algorithms in FPGA, we propose a concept of full frame rate image processing and provide two specific techniques as design guideline, that is convolution processing method based on pixel stream buffering and feature parameters extraction technolo- gy based on the relevance of adjacent frames, by which the hardware logic circuits of most of the space domain image processing algorithms and their random combination can be easily designed and implemen- ted in FPGA and achieve up to the speed in accord with the input frames rate. For verification, the design process of Canny operator is detailedly presented. Experimental results show that the proposed full- frame rate image method prove to be practicable and is characteristic for its high processing speed and modular- ization design, making it particularly suitable for real- time embedded vision systems.