一种改进的基4-Booth编码流水线大数乘法器设计

Design of Pipeline Large Integer Multiplier Based on an Implementation of Radix-4 Modified Booth Encoding

大数乘法器是密码算法芯片的引擎,它直接决定着密码芯片的性能.由此提出了一种改进的基4-Booth编码方法来缩短Booth编码的延时,并提出了一种三级流水线大数乘法器结构来完成256位大数乘法器的设计.基于SMIC0.18μm工艺,对乘法器设计进行了综合,乘法器的关键路径延时3.77ns,它优于同类乘法器.

A large integer multiplier is the engine of cryptography chip and determines the performance of cryptography chip. In this paper, we propose a new implementation of radix-4 modified Booth encoding, which has a shorter delay than methods proposed in previous works. Upon this encoding method, we also propose a new structure of 256-bit three stage pipeline multiplier. After synthesizing based on SMIC 0. 18 um CMOS process, the critical path delay of the multiplier is 3.77 ns, which is superior to that of other multipliers.