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一种基于可配置随机测试生成的多核验证方法

A Method Based on Configurable Random Test Generation for Multi-core Verification
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摘要 多核设计规模和复杂度的不断提高,使功能验证变得越来越具挑战性.通过分析基于模拟仿真的多核验证方法,提出了一种基于可配置随机测试生成的多核cache一致性验证方法.该方法以随机测试生成为基础,通过配置随机生成参数来产生特定结构的多核验证指令流.此指令流的特点是,通过内存地址访问约束和多核同步操作的设置,来达成多核系统执行顺序的准确预测,进而通过自检测指令组的配置来完成自动快速结果比较.实验结果表明,该方法对多核一致性的验证是高效的. As multi-core designs architectural complexity increases, the challenge of verification grows dramatically. Through analyzing the methods of simulation based verification of multi-core designs, in this paper we present a new method based on eonfigurable random test generation to verify multi-core cache coherence. Configurahle random test generation is used to generate specified instruction streams by controlling generation variables. The execution sequence of the instruction stream in multi-core design can be predicted exactly by using memory address accessing constraints and synchronization operation. Further more, the self-checking instruction groups are used to check the simulation results automatically. The experiment result shows that our method is efficient.
作者 罗汉青 梁利平 叶甜春
机构地区 中国科学院微电子研究所
出处 《微电子学与计算机》 CSCD 北大核心 2014年第1期88-91,98,共5页 Microelectronics & Computer
关键词 多核设计 CACHE一致性 指令流配置 同步设置 自检测 multi-core cache coherence random instruction stream synchronization operation sel^checking
分类号 TP302 [自动化与计算机技术—计算机系统结构]
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参考文献8

  • 1Adir A, Shurek G. Generating concurrent test-pro- grams with collisions for multi-processor verification [C]//proceedings of the 7th IEEE International High- Level Design Validation and Test Workshop. Cannes, France: IEEE, 2002 : 77-82.
  • 2Wagner I, Bertacco V. MCjammer: Adaptive Verifica- tion for Multi-core Designs [C]//Proceedings of the Conference on Design, Automation and Test in Eu- rope. EDA Consortium San Jose, CA, USA: ACM, 2008:670- 675.
  • 3Singh P, Landis D L. Test generation for CMP designs [C]//proceeding of Microprocessor Test and Verifica- tion (MTV). Austin, TX:IEEE,2010: 67- 70.
  • 4王朋宇,陈云霁,沈海华,陈天石,张珩.片上多核处理器存储一致性验证[J].软件学报,2010,21(4):863-874. 被引量：13
  • 5Taylor S, Ramey C, Barner C, et al. A simulation- based method for the verification of shared memory in multiprocessor systems[C]//IEEE/ACM ICCAD. [s. l. ] : IEEE, 2001 : 10-17.
  • 6Chen X, Yang Y, Gopalakrishnan G, et al. Reducing verification complexity of amulticore coherence proto- col using assume/guarantee [C]//proceeding of FM-CAD. San Jose, California, USA: IEEE, 2006 : 81- 88.
  • 7Meixner A, Sorin D. Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures[J]. IEEE Transactions on Deperdable and Secure Computing, 2009,6(1) :18-31.
  • 8Manovit C, Hangal S. Efficient algorithms for verif- ying memory consistency[C]//Proc of the 17th ACM Symp on Parallelism inAlgorithms and Architecture. Las Vegas, Nevada, USA.. ACM,2005 : 245-252.

二级参考文献20

  • 1Chatterjee P,Sivaraj H,Gopalakrishnan G.Shared memory consistency protocol verification against weak memory models:Refinement via model-checking.In:Proc.of the 14th Int'l Conf.on Computer Aided Verification (CAV 2002).2002.http://www.cs.utah.edu/formal_verification/papers/cav02paper.pdf.
  • 2Yang Y,Gopalakrishnan G,Lindstrom G,Slind K.Nemos:A framework for axiomatic and executable specifications of memory consistency models.In:Proc.of the 18th Int'l Parallel and Distributed Processing Symp.(IPDPS 2004).2004.http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1302944.
  • 3Gibbons P,Korach E.On testing cache-coherent shared memories.In:Proc.of the 6th ACM Symp.on Parallel Algorithms and Architectures (SPAA'94).1994.http://delivery.acm.org/10.1145/190000/181328/p177-gibbons.pdf?key1=181328&key2=318237 8621&coll=GUIDE&dl=GUIDE&CFID=82133830&CFTOKEN=76647768.
  • 4Gibbons P,Korach E.Testing shared memories.SIAM Journal on Computing,1997,26(4):1208-1244.
  • 5Meixner A,Sorin D.Dynamic verification of sequential consistency.In:Proc.of the 32nd Int'l Symp.on Computer Architecture (ISCA 2005).2005.http://people.ee.duke.edu/～sorin/papers/isca05_dvsc.pdf.
  • 6Meixner A,Sorin D.Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures.In:Proc.of the Int'l Conf.on Dependable Systems and Networks (DSN 2006).2006.http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=& arnumber=1633497&userType=inst.
  • 7Hangal S,Vahia D,Manovit C,Lu J,Narayanan S.Tsotool:A program for verifying memory systems using the memory consistency model.In:Proc.of the 31st Int'l Symp.on Computer Architecture (ISCA 2004).2004.http://ieeexplore.ieee.org/ iel5/9170/29103/01310768.pdf?arnumber=1310768.
  • 8Manovit C,Hangal S.Efficient algorithms for verifying memory consistency.In:Proc.of the 17th ACM Symp.on Parallelism in Algorithms and Architecture (SPAA 2005).2005.http://delivery.acm.org/10.1145/1080000/1074011/p245-manovit.pdf?key1= 1074011&key2=6873378621&coll=GUIDE&dl=GUIDE&CFID=82135957&CFTOKEN=66149051.
  • 9Roy A,Zeisset S,Fleckenstein C,Huang J.Fast and generalized polynomial time memory consistency verification.In:Proc.of the 18th Int'l Conf.on Computer Aided Verification (CAV 2006).Berlin,Heidelberg:Springer-Verlag,2006.503-516.
  • 10Manovit C,Hangal S.Completely verifying memory consistency of test program executions.In:Proc.of the 12th Int'l Symp.on High-Performance Computer Architecture (HPCA 2006).2006.http://ieeexplore.ieee.org/iel5/10647/33614/01598123.pdf? arnumber=1598123.

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微电子学与计算机
2014年 第1期

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