摘要
为了解决寄存器保持时间不满足而引起的短路径问题,提出一种自动修复短时序违反路径的FPGA布线算法。在VPR时序布线算法整体布线布通之后,调用短路径时序分析来获取违反短时序约束的布线连接,然后通过修改代价函数,对每条违反短时序约束的连接进行增量布线,使每条连接的路径延时尽可能达到满足短时序约束所需的延时。实验结果表明,本算法与VPR时序驱动布线算法相比,能够平均修复94.7%的短时序违反路径,而运行时间仅增加了6.8%。
This paper presented a routing algorithm that automatically repaired short-path violations in order to solve short-path problems resulting from holdtime violations in FPGAs. After the execution of VPR timing-driven routing algorithm, the proposed algorithm invoked short-path timing analysis to identify short-path violation connections, and then modified cost function and incrementally rerouted these connections to satisfy short-path constraints. Experimental results demonstrate that the proposed method can repair 94. 7% of short-path violations, while, compared with the VPR, the runtime only increases by 6. 8% on average.
出处
《计算机应用研究》
CSCD
北大核心
2014年第1期66-69,共4页
Application Research of Computers
基金
国家科技重大专项资助项目(2013ZX03006004)
国家自然科学基金资助项目(61106033)