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自动修复短时序违反路径的FPGA布线算法

Automatic repairing short-path violations FPGA routing algorithm
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摘要 为了解决寄存器保持时间不满足而引起的短路径问题,提出一种自动修复短时序违反路径的FPGA布线算法。在VPR时序布线算法整体布线布通之后,调用短路径时序分析来获取违反短时序约束的布线连接,然后通过修改代价函数,对每条违反短时序约束的连接进行增量布线,使每条连接的路径延时尽可能达到满足短时序约束所需的延时。实验结果表明,本算法与VPR时序驱动布线算法相比,能够平均修复94.7%的短时序违反路径,而运行时间仅增加了6.8%。 This paper presented a routing algorithm that automatically repaired short-path violations in order to solve short-path problems resulting from holdtime violations in FPGAs. After the execution of VPR timing-driven routing algorithm, the proposed algorithm invoked short-path timing analysis to identify short-path violation connections, and then modified cost function and incrementally rerouted these connections to satisfy short-path constraints. Experimental results demonstrate that the proposed method can repair 94. 7% of short-path violations, while, compared with the VPR, the runtime only increases by 6. 8% on average.
作者 刘洋 杨海钢 喻伟 蔡刚 徐维涛
机构地区 中国科学院电子学研究所可编程芯片与系统研究室 中国科学院大学
出处 《计算机应用研究》 CSCD 北大核心 2014年第1期66-69,共4页 Application Research of Computers
基金 国家科技重大专项资助项目(2013ZX03006004) 国家自然科学基金资助项目(61106033)
关键词 FPGA 布线 短时序违反路径 代价函数 增量布线 FPGA routing short-path violations cost function incrementally reroute
分类号 TP302.1 [自动化与计算机技术—计算机系统结构] TP301.6 [自动化与计算机技术—计算机系统结构]
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参考文献11

  • 1SHENOY N, BRAYTON R, SANGIOVANNI-VINCENTELLI A. Mini- num padding to satisfy short path constraints[ C ]//Proc of IEEE/ACM International Conference on Computer-Aided Design. Santa Clara: ACM Press,1993:156-161.
  • 2FRANKLE J. Iterative and adaptive slack allocation for performance- driven layout and FPGA routing [ C ]//Proc of the 29th ACM/IEEE Design Automation Conference. Los Alamitos:IEEE Computer Socie- ty, 1992:536-542.
  • 3McMURCHIE L, EBELING C. PathFinder: a negotiation-based per- formance-driven router for FPGAs [ C ]//Proc of the 3 rd International ACM Symposium on Field-Programmable Gate Arrays. New York: ACM Press, 1995 : 111-117.
  • 4MLEXANDER M, ROBINS G. New performance-driven FPGA routing algorithms[J]. IEEE Trans on Computer-Aided Design of Inte- grated Circuits and Systems, 1996,15 (12) : 1505-1517.
  • 5BETZ V, ROSE J. VPR:a new packing, placement and routing tool for FPGA research [ C]//Proc of the 7th International Workshop on Field Programmable Logic and Application. London: Springer, 1997 : 213-222.
  • 6BETZ V,ROSE J,MARQUARDT A. Architecture and CAD for deep- submicron FPGAs [ M ]. Norwell: Kluwer Academic Publishers, 1999.
  • 7RUBIN R, De HON A. Timing-driven pathfinder pathology and reme- diation: quantifying and reducing delay noise in VPR-pathfinder [ C ]//Proc of the 19th International ACM Symposium on Field-Pro- grammable Gate Arrays. New York : ACM Press,2011 : 173-176.
  • 8ROSE J, LUU J, YU Chi-wai, et al. The VTR project: architecture and CAD for FPGAs from verilog to routing[ C ]//Proc of the 20th Interna- tional ACM Symposium on Field-Programmable Gate Arrays. New York : ACM Press,2012 : 77- 86.
  • 9FUNG R, BETZ V, CHOW W. Simultaneous short-path and long-path timing optimization for FPGAs[ C]//Proc of IEEE/ACM International Conference on Computer-Aided Design. Washington DC : IEEE Com- puter Society,2004 : 838- 845.
  • 10FUNG R, BETZ V, CHOW W. Slack allocation and routing to improve FPGA timing while repairing short-path violations [ J]. IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, 2008,27(4) :686-697.

二级参考文献17

  • 1Tuan T, Kao S, Rahman A, et al. A 90nm low-power FPGA for battery-powered applications[C]//Proceedings of the 14th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, 2006:3-11.
  • 2Anderson J H, Najm F N. Switching activity analysis and pre-layout aetivity prediction for FPGAs [C] //Proeeedings of the International Workshop on System-Level Interconnect Prediction, Monterey, 2003:15-21.
  • 3Rose J, Gamal A E, Sangiovanni-Vincentelli A. Architecture of field-programmable gate arrays [J]. Proceedings of the IEEE, 1993, 81(7) : 1013-1029.
  • 4Monteiro J C, Oliveira A L. Finite state machine decomposition for low power [C] //Proceedings of the 35th Annual Conference on Design Automation, San Francisco, 1998:758-763.
  • 5Kim D, Choi K. Power-conscious high level synthesis using loop folding [C]//Proceedings of the 34th Annual Conference on Design Automation, Anaheim, 1997:441-445.
  • 6Kandemir M, Vijaykrishnan N, Irwin M J, et al. Influence of compiler optimizations on system power [J]. IEEE Transactions on Very Large Scale Integration Systems, 2001, 9(6) : 801-805.
  • 7Lamoureux J, Wilton S J E. On the interaction between power-aware FPGA CAD algorithms [C] //Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, 2003:701-708.
  • 8Chen D M, Cong J, Li F, et al. Low-power technology mapping for FPGA architectures with dual supply voltages [C] //Proceedings of the 12th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, 2004:109-117.
  • 9Monteiro J, Devadas S, Ghosh A. Retiming sequential circuits for low power [C]//Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Santa Clara, 1993: 398-402.
  • 10Wilton S J E, Ang S S, Luk W. The impact of pipelining on Energy per operation in field-programmable gate arrays [M] // Lecture Notes in Computer Seience. Heidelberg: Springer, 2004:719-728.

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