基于层次化事件队列的赋值操作应用

Assignment Based on Stratified Event Queue

随着ASIC、SoC和FPGA在工业生产和科研工作中的广泛应用,作为硬件描述语言的Verilog HDL已成为实现集成电路设计的重要方式,而设计师对其中赋值操作的错误使用,也导致了部分设计的不正确.因此,对于Verilog HDL中赋值操作的深入了解也成为解决设计中隐藏问题的瓶颈.基于层次化事件队列,对设计中经常遇到的赋值操作问题进行了深入剖析,并结合工作实际给出了避免设计中竞争问题出现的方法.

With the development of ASIC, SoC and FPGA in research and industry, Verilog HDL has been the main method to design the integrate circuit. For the designer miusing the assignments in Verilog HDL, more and more designs have been with some invisible bugs. That the designers fully understand how the assignments are scheduled in the program has been the main method to solve the bugs. This paper is based on the stratified event queue to detail how the assignment works in design, and gives important coding guidelines to infer correct logic and avoid race condition in the design.