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基于Σ-Δ调制的单比特非线性BP人工神经网络的硬件实现 被引量:1

Hardware implementation of single-bit nonlinear BP neural network based on sigma-delta modulation
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摘要 提出了一种基于∑-△调制(SDM)的单比特BP人工神经网络的硬件实现方法。设计了基于∑-△单比特信号的非线性立方根运算单元,并以此为激活函数单元构建了BP人工神经网络,网络中各神经元的输入输出均为基于∑-△调制的单比特信号。在此基础上实现S函数逼近和网络隐含层的非线性输出。同时采用低环路延时加法器、混合信号乘法器作为关键运算单元,减少了硬件消耗,提高了运算精度。最后在可编程门阵列(FPGA)上实现整个非线性BP人工神经网络,并通过函数逼近的实例验证了该网络的功能。 A new method for implementation of the hardware of single-bit feed-forward BP artificial neural networks by using sigma-delta modulation (SDM)was presented. The nonlinear cube-root calculation unit based on single-bit streams was designed, and by taking it as the activation function, the BP artificial neural network was constructed. The signals from the network' s input and output of each neuron were represented by sigma-delta modulated singlebit streams. As the activation function in the hidden layer should be nonlinear, the log-Sigmoid squashing function approximation was obtained through the design of a cube-root computation module based on sigma-delta bit stream. A little-loop-delay adder and a hybrid-signal multiplier were also presented as the key function elements of the sys- tem to offer low hardware consumption and high precision. The neurons and the whole BP neural network were implemented and simulated on a field programmable gate array(FPGA). Two examples of function approximation successfully demonstrate that the sigma-delta bit stream technique is viable for the hardware implementation of BP neu- ral networks.
出处 《高技术通讯》 CAS CSCD 北大核心 2013年第12期1316-1322,共7页 Chinese High Technology Letters
基金 国家自然科学基金(61076118)资助项目
关键词 单比特 人工神经网络 非线性 BP网络 SIGMA-DELTA 可编程门阵列(FPGA) single-bit, artificial neural network, nonlinear, BP network, sigma-delta, field programmable gate array (FPGA)
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  • 1Zhang D, Li H, Foo S Y. A simplified FPGA implementation of neural network algorithms integrated with stochastic theory for power electronics applications. In: Proceedings of the 31 st Annual Conference of the IEEE Industrial Electronics Society, Raleigh, USA, 2005. 1018-1023.
  • 2Hu H, Huang J, Xing J G, et al. Key issues of FPGA implementation of neural networks. In: Proceedings of the 2nd International Symposium on Intelligent Information Technology Application, Shanghai, China, 2008.259-263.
  • 3Himavathi S, Anitha D, Muthuramalingam A. Feedforward neural network implementation in FPGA using layer multiplexing for effective resource utilization. IEEE transactions on neural networks, 2007, 18(3): 880-888.
  • 4Katao T, Hayashi K, Fujisaka H, et al. Sorter-based Sigma-delta domain arithmetic circuits. In: Proceedings of the 18th European Conference on Circuit Theory and Design, Seville, Spain, 2007. 679-682.
  • 5Pneumatikakis A, Deliyannis T. Direct processing of Sigma-delta signals. In: Proceedings of the 3rd IEEE International Conference on Electronics, Circuits, and Systems, Rodos, Greece, 1996.13-16.
  • 6Ng C W, Wong N, Ng T S. Bit-stream adders and multipliers for tri-level Sigma-delta modulators. IEEE Transactions on Circuit and System - I1: Express Briefs, 2007, 54(12): 1082-1086.
  • 7Ng C W, Wong N, Ng T S. Quaddevel bit-stream adders and multipliers with efficient FPGA implementation. Electronics Letters, 2008, 44(12): 722-724.
  • 8Hayashi K, Katao T, Fujisaka H, et al. Piecewise linear circuits operating on first-order multi-level and second-order binary Sigma-delta modulated signals. In: Proceedings of the 18th European Conference on Circuit Theory and Design, Seville, Spain, 2007.683-686.
  • 9Liang Y, Wang Z G, Meng Q, et al. Design of high speed high SNR bit-stream adder based on EA modulation. Electronics Letters, 2010, 46(11):752-753.
  • 10Fujisaka H, Kurata R, Sakamoto M, et al. Bit-stream signal processing and its application to communication systems, lEE Proceedings-Circuits, Devices, and Systems, 2002, 149(3): 159- 166.

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