基于TSPC的4/5双模前置分频器设计

Design of a Divided by 4 /5 Prescaler Based on TSPC

针对无线传感网络对射频电路高速、低功耗方面日益增长的性能要求,设计了一款用于高频锁相环中的高速、低功耗4/5双模前置分频器。在分析真单相时钟(TSPC)电路工作原理的基础上,指出了该电路结构存在的两个主要缺点,并结合器件工艺和物理给出了相应的版图优化解决方法。然后,采用SMIC 0.18μm标准CMOS工艺,设计了一款基于这种改进后的真单相时钟电路的集成4/5双模前置分频器。在版图优化设计后利用Cadence Spectre进行了后仿真验证,结果表明,在直流电源电压1.8 V时,该4/5双模前置分频器的最高工作频率可达到3.4 GHz,总功耗仅有0.80 mW。该4/5双模前置分频器的最低输入幅值为0.2 V时,工作频率范围为20 MHz^2.5 GHz,能够满足面向无线传感网络应用的锁相环(PLL)的高速、低功耗性能要求。

As for the overgrowing demand of the wireless sensor network on high speed anO low power RF circuit, a prescaler with high speed and low power divided by 4/5 was designed for application in the high frequency phase locked loop （PLL）- Based on the analysis of the operation principle of true single phase clock （TSPC） , the two main shortcomings were pointed out, and the corresponding solu- tions were proposed by considering the devices physics and process. Then, a prescaler with high speed and low power integrated divided by 4/5 was designed in SMIC 0. 18μm standard CMOS technology. The design was based on the improved TSPC circuit and oriented for the high frequency phase locked loop （PLL） application. After the layout of the integrated prescaler was designed and optimized, a post simu- lation was done with Cadence Spectre to validate its performances. The results indicate that the maximum frequency of the proposed prescaler is about 3.4 GHz with 1.8 V DC power supply, the total power loss is only about 0. 80 mW and the operating frequency of the optimized integrated prescater ranges from 20 MHz to 2.5 GHz with 0.2 V input signal of sinusoid wave.. Therefore, the designed prescaler is capa- ble of meeting the high speed and low power loss requirements of phase locked loop （PLL） applied to wireless sensor network.