含TSV结构的3D封装多层堆叠Cu/Sn键合技术

Multilayer Stack Cu /Sn Bonding Technology for 3D Packaging with TSV

研究了利用Cu/Sn对含硅通孔(TSV)结构的多层芯片堆叠键合技术。采用刻蚀和电镀等工艺,制备出含TSV结构的待键合芯片,采用扫描电子显微镜(SEM)对TSV形貌和填充效果进行了分析。研究了Cu/Sn低温键合机理,对其工艺进行了优化,得到键合温度280℃、键合时间30 s、退火温度260℃和退火时间10 min的最佳工艺条件。最后重点分析了多层堆叠Cu/Sn键合技术,采用能谱仪(EDS)分析确定键合层中Cu和Sn的原子数比例。研究了Cu层和Sn层厚度对堆叠键合过程的影响,获得了10层芯片堆叠键合样品。采用拉力测试仪和四探针法分别测试了键合样品的力学和电学性能,同时进行了高温测试和高温高湿测试,结果表明键合质量满足含TSV结构的三维封装要求。

A Cu/Sn multilayer stack bonding technology for 3D-TSV system-in-packaging was studied. Some key technologies such as through silicon via （TSV） technology and electroplating process were used to prepare the sample chip with TSV. The morphology and filling effect of TSV were analyzed using scanning electron microscope （SEM）. Cu/Sn low-temperature bonding mechanism was studied and the process was optimized to determine the best condition to form the best bond layer. The bonding temperature was 280 ℃ , the bonding time was 30 s, the annealing temperature was 260 ℃ and the annealing time was 10 min. Finally, multilayer stack Cu/Sn bonding technology was analyzed. The atomicity ratio of Cu and Sn in bonding layer was determined using energy disperse spectroscopy （EDS）. The influence of the Cu layer thickness and Sn layer thickness on the stack bonding process was researched and eventually l0 layers stack samples were obtained. The mechanical and electrical properties of the bonding samples were tested using tensile tester and four probe method, and high temperature test and high temperature and high humidty test were carried out. The test results show that a reliable stack bonding technology could be used for 3D packaging with TSV.