FPGA片间万兆可靠通信的设计与实现

Design and Implementation of 10-Gbit/s Reliable Intra-FPGA Communication

随着云计算技术的发展,采用FPGA作为协同加速成为其发展的一个趋势,如何设计与实现FPGA片间的高速通信是该研究方向的一个热点。研究了FPGA万兆通信的物理层、MAC层的实现机制,在通信协议可靠传输方面实现了MAC层的流控以及错误包检测功能。仿真以及实际平台测试表明,该通信协议能够实现FPGA片间万兆的线速通信。

FPGA have already been successfully employed since the rapid growth of cloud computing,so that many researches focus on the reliable intra- FPGA communication . This paper adopts the bad frame filter technique and flow control technique to realize the reliable muhi-FPGA communication after in- troducing the PHY and MAC layer design of 10 G Ethemet. The simulation and experimental results show that communication speed can reach 10 Gbit/s.