应用于CMOS图像传感器的高速列级ADC

A high-speed column-parallel ADC for CMOS image sensor

提出了一种应用于CMOS图像传感器中的高速列级ADC。采用单斜ADC与TDC结合的方法,先将模拟电压信号转换为成比例的时间段,再通过TDC量化为相应的数字码,其转换时间主要取于TDC的量化范围,解决传统列级单斜ADC转换速率低的问题。设计采用0.18μm CMOS工艺。Spectre仿真表明,在模拟电路3.3 V、数字电路1.8 V的供电电压下,ADC的信噪失真比(SNDR)达到51.2 dB,整体功耗为1.76 mW,列级电路功耗为236.38μW,采样频率为1 MS/s,输入信号范围为1.6 V,满足CMOS图像传感器系统的应用要求。

This paper presents a high-speed column-parallel analog to digital converter with time to digital converter to over- come the long conversion time problem in conventional column-parallel single slope ADC for CMOS image sensors. The main prin- ciple is to get the time interval which is proportional to the input signal. Then the time interval is digitized by TDC. Through Spectre simulation, the 10 bit ADC designed in 0.18 μm CMOS process achieves 1 μs conversion time, 1.6 V input signal range and the SNDR of 51.2 dB. The total power consumption of the proposed ADC is 1.76 mW including 236.38 p,W power consumption per colmnn.