摘要
该文针对大学计算机专业《数字逻辑设计》课程中脉冲异步时序逻辑电路的教学提出改进,将触发器的特性方程和时钟条件加以综合设计,采用仿真软件对设计方案进行验证,并示范在脉冲异步时序电路设计中的运用,有助于学生理解和掌握脉冲异步时序电路的设计和仿真方法。
In this paper, based on the teaching of the university computer professional digital logic design course, the synthesis of Flip-flop＇s characteristic equation and clock＇s function is put forward, the logic circuits is simulated by EDA tools to verify its correct- ness, and the demonstration of using Multisim is applied to an example of pulse-mode asynchronous sequential circuits, it will help student to understand and grasp the design and verify method for pulse-mode asynchronous circuits.
出处
《实验科学与技术》
2013年第6期218-220,277,共4页
Experiment Science and Technology
关键词
数字逻辑设计
仿真
脉冲异步时序
时钟信号
digital logic design
simulation
pulse-mode asynchronous circuits
clock signals
