基于FPGA的交流采样同步倍频算法及实现

FPGA Based Alternating Current Sampling Synchronous Frequency Multiplication Algorithm and Implementation

为了保证电能质量监测系统中电力参数的准确性,需要对其进行交流采样。而在交流采样中,需要进行同步倍频。传统的由锁相环CD4046做成的频率跟踪电路来进行倍频,很难进行倍频倍数的改变。本文利用verilog HDL语言,针对传统倍频电路的限制,通过计数分频的方式实现了抖动信号源、任意低频、任意高倍的倍频算法。最后通过matlab仿真,以及提供的FPGA器件搭建硬件电路后,经测试证实了算法的正确性可用性。

The power parameter needs to be alternating current sampld so as to ensure its accuracy in power quality monitoring system. In AC（alternating current） sampling, however, synchronization frequency doubling has to be adopted. It is difficult to change the times of the multiple frequency doublings by frequency tracking circuit composed of phase lock loop CD4046 in traditional ways. In this paper, a new frequency doubling algorithm has been proposed for any low frequency and any high multiple of the jitter signal source through the way of counting frequency division based on verilog HDL language, so as to release the limitation of FPGA internal PLL. Finally, simulating results based on matlab confirm the correctness and availability of the algorithm..