一种高速数据接口的设计方法

Design on High-Speed Data Interface

数字通信业务的蓬勃发展对核心元器件的接口带宽提出了越来越高的要求。目前主流元器件解决方案中,主要采用高速串行接口(SerDes)和低压差分接口LVDS实现,但SerDes接口IP价格昂贵。提出一种采用纯数字的采样时钟相位调整和字调整方式,可对源同步数据进行准确采样和恢复,可替代SerDes接口实现10 Gb/s 16通道LVDS高速接口。本设计方法不依赖于具体的集成电路生产工艺,所使用的IP核是国内主流芯片厂商的主流工艺上都可提供的,可以较低的成本在ASIC芯片上实现高速数据传输接口,满足芯片国产化需求。

With the rapid development of digital communication, the even higher request for interface band- width of core components is raised. The present solutions for mainstream components mostly use SerDes （high-speed serial interface） and low voltage differential interface LVDS in implementation, but the SerDes interface IP is rather expensive. A pure digital sampling clock phase and word adjustment mode for accurately, sampling and recovering the source synchronous data is proposed, and this mode could replace SerDes in implementing LVDS high-speed interface of interface 10 Gb/s 16 channel. This method, with no dependence on specific IC technology, could use the IP core produced in mainstream technology and supplied by principal chip manufacturers at home, and thus the cost to achieve high-speed data transmis- sion interface on ASIC chip could be reduced and the domestic demand be satisfied.