(7,3)循环码编解码电路的EDA设计

EDA Design of Encoding and Decoding Circuit for (7,3) Cyclic Code

大规模集成电路一般只提供内部框图,不提供具体电路,这给设计者对可编程器件硬件开发设计带来困难。基于此,介绍常用的信道编码——(7,3)循环码编码解码逻辑电路的EDA设计,用VHDL语言对(7,3)循环码编码器和解码器进行描述,用Quartus II软件进行仿真测试。从仿真结果看,电路完全符合要求,可以烧写成芯片。

There is only the internal block diagram in the very large integrated circuit, but there is not the specific circuit. It is difficult for the designer to design programmable hardware devices. This paper mainly introduces the EDA design of circuit for （7,3） cyclic code and encoding and decoding coding which is often applied in data transmission. It simply describes the （7,3） coder with VHDL language, and simulates it with the software of Quartus II. As a the requirements and load into chip from the simulation results. cyclic result, with the channel code encoder and de- this circuit can meet