摘要
对取样锁相环的工作原理进行了研究,分析了取样鉴相器的数学模型,并对数字倍频锁相环与取样锁相环的相位噪声性能进行了分析和对比,在实际电路中加入了扩捕电路,最终设计和实现了可满足工程应用的取样锁相环。
In this paper ,the Sampling Phase Lock Loop was investigated and the mathematics model of the Sampling Phase detector was analyzed. Also the phase noise of the digital PLL and the Samphng PLL was ana- lyzed and compared. In the actual circuit,a expansion capturing circuit was involved.And finally a band Sam- piing Phase Lock Loop was designed and implemented successfully.
出处
《通信对抗》
2013年第4期22-26,共5页
Communication Countermeasures
关键词
取样锁相环
超低相噪
扩捕电路
sampling phase lock loop
extra low phase noise
expansion capturing circuit
