摘要
针对空间应用对固态存储器中ECC校验在计算速度和纠错能力上的要求,提出了一种应用在NAND Flash控制器中的高速并行BCH编译码器。文中采用了一种独特的译码器架构,并改进了计算伴随式的算法,先利用编码电路计算出伴随多项式,再利用译码电路计算出伴随式。与直接计算出伴随式的译码器相比,虽然译码时间略有增加,但却能明显减少资源的占用量。结合采用其他一些节省资源和提高运行速度的措施,使该译码器的设计更适应空间应用的需要。
Based on the requirements of operating rate and correction capability for ECC of solid state memory for space application, a new architecture of parallel BCH encoder and decoder applied in NAND Flash Controller is presented. Design a new architecture of BCH decoder, and improve syndrome calculation algorithm. It utilizes encoder to calculate out syndrome polynomial first, and then uses decoder to calculate out the syndrome. Compared with other decoder which directly calculates out the syndrome, although it has a little decoding time increasing, could significantly reduce the usage of resources. This design combined with some other measures to save resources and improve speed, could better meet the demands of space application.
出处
《计算机技术与发展》
2014年第1期179-183,共5页
Computer Technology and Development
基金
总装备部预研计划项目(xxxx04013205)
