摘要
介绍硬件描述语言Verilog-HDL。通过与传统的数字逻辑系统的设计方法进行比较,展现了硬件描述语言Verilog-HDL设计数字逻辑电路的优越性。
In this paper, Verilog HDL---a hardware description language is introduced. The process of designing digital logic system by verilog HDL is presented, compared with the traditional digital logic system design method.
出处
《计算机工程》
CAS
CSCD
北大核心
2000年第12期110-112,共3页
Computer Engineering