利用YAY最终解决VHDL中歧义文法问题的方案

Solution to Ambiguities Elimination of VHDL by YAY

提出了一种使用新的编译器产生工具YAY来编写VHDL语法分析器的方法，实践证明，用这种方法设计的语法分析器完全解决了VHDL中歧义文法的问题而且其对应的代码效率较高，可读性较好。

A synthesis system based on VHDL usually consists of parser, optimizer and inferencer. The parsers of some existing VHDL synthesis systems are commonly generated by YACC. However, VHDL definitions have many ambiguities, the codes of grammar description of VHDL with YACC are low efficient because many measures must be adopted to avoid conflicts in parsing. In this paper, a new technique to generate a VHDL parser by YAY, another kind of compiler generator, is introduced. When using YAY, programmers can solve the problem of ambiguity elimination easily.