载波跟踪环路鉴别器的改进设计及FPGA实现

An Improved Design of Discriminators in Carrier Tracking Loop and Its FPGA Implementation

目前GPS接收机载波跟踪环路往往采用易于硬件实现，但精度不高、跟踪速度慢的鉴别器。针对该现状，在现有CORDIC算法基础上加以改进，并在FPGA上完成了二象限反正切鉴相器和四象限反正切鉴频器的设计。在原有CORDIC算法上加入象限转换和相位转换功能，使反正切计算范围扩大至-180°～180°；通过增加鉴频器门限设定，消除了导航电文翻转带来的误差。该设计方案使载波跟踪鉴别器共用一个反正切模块，减少了硬件资源。最终仿真结果表明：改进后的鉴别器提高了鉴相与鉴频的精度，加快了稳定跟踪的速度。

Discriminators in carrier tracking loop of GPS receiver are often good at hardware design,but poor at accuracy and tracking speed .Aiming at this actuality,we made an improvement based on the existing CORDIC （ coordinate rotation digital computer ） algorithm,and achieved the design of a two-quadrant arctangent phase discriminator and a four-quadrant arctangent frequency discriminator in FPGA .The functions of quadrant conversion and phase conversion were added to the original CORDIC algorithm,thus the arctangent calculation range was expanded to-180°~180°.The error caused by navigation message inversion was eliminated by adding threshold setting to discriminators .Because it made the phase discriminator and the frequency discriminator share the same arctangent module,so it was able to reduce hardware resources .The simulation results indicated that the improved discriminators can achieve better accuracy of discriminating phase and frequency,and can also accelerate the stable tracking speed .