采用Karatsuba算法在FPGA上实现双精度浮点乘法

Implement of double-precision floating-point multiplier based on FPGA using Karatsuba algorithm

双精度浮点运算广泛应用于数值计算和信号处理中,在IEEE754标准中实现两个双精度浮点乘法需要一个53 bit×53 bit的尾数乘法器,这样的一个乘法器若采用FPGA实现需要大量的硬件资源。将Karatsuba算法应用于浮点运算器中,采用FPGA实现了一个浮点乘法器,与传统方法相比该乘法器占用硬件资源较少。

The double-precision floating-point multiplication is widely used in the numerical calculation and signal processing. In the IEEE754 standard,a double-precision floating-point multiplication requires a mantissa multiplier of 53 bit × 53 bit,which uses a lot of FPGA resource. It is proposed that Karatsuba algorithm is applied to the double-precision floating-point multiplication,and a floatingpoint multiplier is realized based on FPGA. Compared with the traditional method,this multiplier consumes less hardware resource.