摘要
介绍了一个高速多通道SerDes发送端系统的设计.设计采用65nm CMOS工艺,单通道数据率为10Gb/s.数据通道由一个全速率并串转换Mux电路和一个CML驱动器组成:在并串转换电路的高速部分,为了节省功耗和面积,采用TSPC型的锁存器和触发器代替CML型结构;输出驱动器采用CML结构,并加入一个四抽头的前馈均衡电路以减小数据信号码间串扰的影响;最后为了使信号能够无反射地进行传输,设计了阻抗匹配电路.
In this paper, a design for the transmitter system of muti-channel high speed SerDes is presented. It＇s realized in 65 nm CMOS process and the data rate of a single lane is 10 Gb/s. The data lane circuit consints of a fullrate MUX and a CML driver; The MUX is adopted the structure with TSPC latches and TSPC D-flip-flops （DFF） instead of CML circuits in the high speed stages to save power and area. The diver is made of CML structure, and a 4 tap feed-forward equalization （FFE） is applied in the driver to reduce the influence of ISI; Finally, the impedance matching circuit is used to avoid signal reflection in the channel.
出处
《微电子学与计算机》
CSCD
北大核心
2014年第2期14-17,22,共5页
Microelectronics & Computer
基金
国家科技重大专项"核高基"项目(2011ZX01034-002-002-001)
