期刊文献+

多模GNSS接收机中BCH(15,11,1)并行解码算法 被引量:3

BCH(15,11,1)Parallel Decoding Algorithm in Multi-mode Satellite Navigation Receiver
下载PDF
导出
摘要 北斗卫星导航系统B1信号使用BCH(15,11,1)编码,其空间信号接口控制文件提供的解码器由反馈移位寄存器组成,需要多个时钟周期解码,且与其他卫星导航系统解码结构不兼容.为此推导了BCH(15,11,1)的监督矩阵和校正子,设计了仅使用组合逻辑构成的解码器.仿真结果表明该解码器能够在一个时钟周期内完成解码,实现和操作都更简单,且与GPS、GLONASS卫星导航系统的解码器结构一致,简化了多模卫星导航接收机的解码设计. The B1 signal of BeiDou navigation satellite system is coded by BCH(15,11, 1), and the decoder provided by the BeiDou's ICD is based on the feedback shift register. The decoder requires multiple clock cycles, and is not compatible with other satellite navigation system. Therefore, based on the derivation of check matrix and syndrome of BCH(15,11,1), a decoder based on combinational logic is proposed by this paper. The simulation results show that this decoder can work in one clock cycle, and is easily implemented. The structure of this decoder is same as the GPS and GLONASS's, and simplify the design process of multi-mode GNSS receiver.
出处 《微电子学与计算机》 CSCD 北大核心 2014年第2期50-53,共4页 Microelectronics & Computer
基金 中国第二代卫星导航系统重大专项多模导航型基带芯片(2011GFZX03030204)
关键词 多模卫星导航接收机 北斗卫星导航系统 BCH(15 11 1)解码 GNSS receiver BeiDou navigation satellite system, BCH(15,11,1) decode
  • 相关文献

同被引文献20

  • 1赵华,殷奎喜.(15,7)BCH码编译码器的VHDL设计[J].现代电子技术,2004,27(20):100-101. 被引量:7
  • 2王新梅 肖国镇.纠错码-原理与方法[M].西安:西安电子科技大学出版社,2001..
  • 3辛明瑞.面向空间应用的容错RISC处理器体系结构研究[D].西安:西北工业大学,2006.
  • 4Prasad K,Raian B S. A construction of matroidal errorcorrecting networks[C]//ISITA, 2012. USA: Hawaii, 2012 : 401-405.
  • 5Son Hoang Dau, Skachek V, Yeow Meng Chee. Error correction for index coding with side information[J]. IEEE Transactions on Information Theory, 2013, 59 (3)..1517-1531.
  • 6Zhen Wang, Hierarchical decoding of double error cor- recting codes for high speed reliable memories[C]// Design Automation Conference (DAC). USA: Austin, 2013 .. 1-7.
  • 7中国卫星导航系统管理办公室.北斗卫星导航系统空间信号接口控制文件公开服务信号(2.0版)[Z].2013.
  • 8Baumann R C. Soft Errors in advanced semiconductor devices - Part 1: The three radiation source [J] . IEEE Transactions on Device and Materials Reliabili- ty, 2001, 1(1):17-22.
  • 9Radaelli D, Puchner H, Skip Wong, et al. Investiga- tion of multi-bit upsets in a 150 nm technology SRAM device [ J ]. IEEE Transactions on Nuclear Science, 2005,52(6) : 2433-2437.
  • 10Alaa R Alameldeen, Ilya Wagner, Zeshan Chishti, et al. Energy-Efficient Cache Design Using Variable- Strength Error-Correcting Codes[C]// proceedings of the 38th annual international symposium on Computor architecture. New York,NY, USA. 2011.461-472.

引证文献3

二级引证文献5

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部