期刊文献+

双输出FPGA基本逻辑单元结构的布局布线影响研究

Study on the Place and Route Effects of Dual-output FPGA Basic Logic Elements Structure
下载PDF
导出
摘要 FPGA基本逻辑单元结构对其性能有着巨大的影响.采用实验的方法,基于三种不同的FPGA内基本逻辑单元(BLE)结构,分别对一系列的基准电路进行装箱和布局布线,研究了不同BLE结构对FPGA布局布线性能的影响.研究揭示了不同BLE结构对布局质量,布局、布线延时和面积有较大的影响,BLE_C结构在布局、布线延时和面积上有较好的优化效果.实验结果对FPGA的结构设计以及相应EDA工具的设计具有参考意义. FPGA basic logic elements structure has a huge impact on its performance. By experimental method, a series of benchmark circuits to be packed, placed and routed, and study the place and route effects of the different structures based on three different FPGA basic logic elements (BLE) structure. Our research shows that different BLE structures have a large impact on placement cost, place and route's delay, and area. BLE_C structure has better optimization results in placement, routing delay and area. The experimental results have some reference value to FPGA architecture designand EDA tools design.
出处 《微电子学与计算机》 CSCD 北大核心 2014年第2期146-152,共7页 Microelectronics & Computer
基金 国家自然科学基金项目(61072135 60788402) 武汉市科技攻关项目(201110921295)
关键词 基本逻辑单元 理性可编辑门陈列 计算机辅助设计 BLE FPGA CAD VPR placement and routing
  • 相关文献

参考文献23

  • 1施小祥,段振华,动态可重构FPGA的布局布线算法研究[D].西安:西安电子科技大学,2007.
  • 2Betz V, Rose J, Marquardt A. Architecture and CAD for deep-submicron FPGAs[M]. Norwell, MA, USA: Kluwer Academic Publishers, 1999.
  • 3Brown S, Francis R, Rose J, et al. Field-programma- ble gate arrays[M]. Norwell, MA, USA: Kluwer Aca- demic Publishers, 1992.
  • 4Ian Kuon, Jonathan Rose. Area and delay trade-offs in the circuit and architecture design of FPGAs[C]// Proceedings of the 16th international ACM/SIGDA Symposium on Field Programmable gate arrays. New York, N Y,USA: ACM,2008.. 149-158.
  • 5汪宇,王伶俐,童家榕.一种新型FPGA逻辑单元结构的装箱工具[J].复旦学报(自然科学版),2006,45(4):529-532. 被引量:3
  • 6Marquardt A, Betz V, Rose J. Using cluster-based logic blocks and timing-driven packing to improve FP- GA speed and density[C]//Proc Intl Symp on FPGAs. Monterey, CA.. IEEE, 1999 .. 37-46.
  • 7Liu Y, Jiang X, Sun S,et al. An efficient FPGA pack- ing algorithm based on simple dual-output basic logic elements[C]// Proc of the IEEE 8th International Conference on ASIC (IEEE ASICON 2009), Chang- sha, China.- IEEE, 2009.
  • 8倪刚,童家榕.通用的FPGA逻辑映射方法研究[D].上海:复旦大学,2006.
  • 9Rose J, Francis R J, Lewis D, et al. Architecture of field-programmable gate arrays: the effect of logic functionality on area efficiency[J]. IEEE Journal of Solid-State Circuits, 1990, 25(5) : 1217-1225.
  • 10Kouloheris J, E1 Gamal A. FPGA Area vs. Cell gran- ularity - PLA Cells[J]. Foundation and Trends in Elec- tronic Design Automation, 2008,2(2) : 135-253.

二级参考文献10

  • 1Ahmed E, Rose J. The effect of LUT and cluster size on deep-submicron FPGA performance and density [J].IEEE Trans on V-LSI,2004,12(3) : 288-298.
  • 2Altera Inc. Stratix II Device Family Data Sheet [DB/OL]. (2005-12-10) [ 2006-03-01 ]. http://www.altera.com. cn/litera- ture/hb/stx2/stx2_sii5v1_01, pdf.
  • 3Xilinx Inc. Virtex-II Platform FPGAs: Complete Data Sheet [DB/OL]. (2005-03-01) [2006-03-01]. http://direct.xilinx. - - com/bvdocs/publications/ds031.pdf.
  • 4Sentovich E M,Singh K J, Lavagno L, et al. SIS: A system for sequential circuit analysis [R]. USA: University of California, Berkeley, 1992.
  • 5Cong J, Ding Y. Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs [J]. IEEE Trans On CAD, 1994,13(1) : 1-12.
  • 6Betz V, Rose J. Cluster-based logic blocks for FPGAs: Area-efficiency vs. input sharing and size [C]//Proceedings of the 1997 IEEE CICC. Santa Clara, USA: IEEE Press, 1997 : 551-554.
  • 7Betz V,Rose J. VPR: A new packing, placement and routing tool for FPGA research [C] //Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications. London, UK. Springer-Verlag,1997. 213-222.
  • 8王元.0.18μmFPGA系统结构设计与实现[D].上海:复旦大学微电子学系,2005.
  • 9Yang S. Logic synthesis and optimization benchmarks user guide [R]. Version 3.0. USA: Microelectronics Center of North Carolina, 1991.
  • 10顾晓东,许胤龙,陈国良,顾钧.调和装箱算法的平均性能分析[J].计算机学报,2001,24(5):548-552. 被引量:4

共引文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部