一种减小版图共模偏差的方法

A method of reducing the common mode deviation in layout

在版图设计过程中经常会遇到差分输出信号共模点存在偏差的问题。以带共模反馈(CMFB)结构的两级运算放大器为例,对版图分别提取寄生电容C+CC和寄生电阻R进行后仿,对比后仿结果,验证了共模偏差主要是由于寄生电阻的影响。根据后仿结果,采用Calibre软件对版图寄生电阻R进行筛选,找到了影响版图共模点偏差的主要走线,通过将该走线改为并联的形式来减小寄生电阻,使输出差分信号共模偏差由0.172 3 mV下降到15.559μV。

The common mode deviation of differential output signals is commonplace during the layout design process. A two-stage operational amplifier with common feed-back（CMFB）structure is taken for example,the parasitic capacitors C＋CC and parasitic resistors R of the layout are extracted to have post-simulation,through comparison,it is proved that the common mode deviation is mainly effected by parasitic resistors. According to the result,the parasitic resistor R of layout is screened by Cali-bre,and the main line affects the common mode deviation is. The common mode deviation of the differential output signals is re-duced from 0.172 3 mV to 15.559 μV by decreasing the parasitic resistors through changing the lines into parallel connection.