基于FPGA的高速Viterbi译码器设计与实现

Design and Realization of High Speed Viterbi Decoder on FPGA

Viterbi算法是卷积码最常用的译码算法。在卷积码约束长度较大 ,译码时延要求较高的场合 ,如何实现低硬件复杂度的Viterbi译码器成为新的课题。本文提出新颖的Viterbi路径权重算法、双蝶形译码单元结构、高效的状态度量存储器等技术 ,使Viterbi算法充分和FPGA灵活的片内存储和逻辑单元配置方法相结合 ,发挥出最佳效率。用本算法在 32MHz时钟下实现的 2 56状态Viterbi译码器译码速率可达 4 0 0Kbps以上 ,且仅占用很小的硬件资源 ,可以方便地和Turbo译码单元等集成在单片FPGA上 ,形成单片信道译码单元。

Viterbi algorithm is the optimal decoding scheme for convolutional codes. In the cases when large constrain length and low decoding delay are both demanded, how to realize Viterbi decoder at low hardware cost becomes a new challenge. This paper presents some new methods in the design, taking advantage of the versatile configuration of FPGA. These methods are new branch weight algorithm, double butterfly decoding unit structure, uniform state weight memories, etc. A 256 state Viterbi decoder has been implemented on a FPGA, achieving above 400kbps decoding speed under a 32MHz system clock.