摘要
针对目前存在的缩1码模2n＋1加法器的优缺点,设计出一个有效的基于进位选择的缩1码模2n＋1加法器.在模加法器的进位计算中,采用进位选择计算代替传统的进位计算,进位计算前缀运算量明显减少.分析和实验结果表明,对于比较大的n值,进位选择缩1码模2n＋1加法器在保持较高运算速度的前提下,有效地提高了集成度.
An efficient diminished-one modulo 2n ＋ 1 adder is proposed. The diminished modulo adders are de- signed with a sparse parallel-prefix carry computation stage, and only some of the carries of the modulo 2n ＋ 1 addition is computed. The carry computation tors. The analytical and experimental results be implemented in smaller area compared to ficiently wide operands. unit is far simpler, since it requires significantly less prefix opera- indicate that the resulting diminished-one modulo 2n ＋ 1 adder can earlier proposals, while maintaining a high operation speed for suf-
出处
《测控技术》
CSCD
北大核心
2014年第2期127-129,共3页
Measurement & Control Technology
基金
广东省自然科学基金重点项目(S2011020002735)
广东省教育部产学研结合项目(2011A090200088)
关键词
余数系统
模加法器
缩1码
VLSI
residue number system（RNS）
modulo adder
diminished-one
VLSI
