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一种组合逻辑环转化方法

Method for transforming cyclic circuits into acyclic equivalents
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摘要 组合逻辑环能够减少电路逻辑资源,降低电路功耗,但是其难以被静态时序分析工具分析和计算,且难以生成功能验证向量和自动测试图形向量.针对此问题,提出一种组合逻辑环转化方法,以解决硬件描述语言以及高级语言逻辑综合阶段所面临的组合逻辑环拆分问题.不同于采用三值仿真策略的现有文献,引入了布尔可满足引擎对组合逻辑环电路进行了表征,使用静态逻辑蕴涵完成了环形电路的拆分.同时,根据环形电路的形成机理,提出了拆分组合逻辑环结构的规则,用于冗余向量优化以及非环电路的逻辑推理.实验结果表明,这种算法能够正确地拆分组合逻辑环结构,且转化时间短,转化后的电路规模小. The cyclic circuit is capable of reducing the area and power consumption, but it is difficult for tools such as static timing analyzers to analyze and compute. Furthermore, the simulation and DFT for the cyclic circuit are more expensive and complicated. Thus, a method for transforming cyclic circuits into aeyelic equivalents based on the SAT （Boolean Satisfiability） is presented in this paper in order to remove the unwanted cycles in the high- level synthesis process. Different from the available researches, the SAT and static logic implication are introduced in this paper. Meanwhile, by analyzing the structure and mechanism of the cyclic circuits, some novel rules are presented to obtain the aeyelic equivalents more precisely and effectively. Experiments are performed in our scientific research projects and the IPs which come from Opencore. And the transforming time and the area are decreased by 280% and 16%.
作者 邸志雄 史江义 马佩军 张译 袁莉 郝跃 许钊
机构地区 西安电子科技大学宽带隙半导体国家重点实验室
出处 《西安电子科技大学学报》 EI CAS CSCD 北大核心 2014年第1期75-80,共6页 Journal of Xidian University
基金 中央高校基本科研业务费专项资金资助项目(K5051325010)
关键词 组合逻辑环 逻辑综合 SAT引擎 静态逻辑蕴涵 cyclic circuit synthesis Boolean Satisfiability（SAT） static logic implication
分类号 TP391.72 [自动化与计算机技术—计算机应用技术]
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参考文献22

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西安电子科技大学学报
2014年 第1期

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