高性能70nm CMOS器件(英文)

High Performance 70nm CMOS Devices

首次在国内成功地制作了栅长为 70 nm的高性能 CMOS器件 .为了抑制 70 nm器件的短沟道效应同时提高它的驱动能力 ,采用了一些新的关键工艺技术 ,包括 3nm的氮化栅氧化介质 ,多晶硅双栅电极 ,采用重离子注入的超陡倒掺杂沟道剖面 ,锗预无定形注入加低能注入形成的超浅源漏延伸区 ,以及锗预无定形注入加特殊清洗处理制备薄的、低阻自对准硅化物等 . CMOS器件的最短的栅长 (即多晶硅栅条宽度 )只有 70 nm,其 NMOS的阈值电压、跨导和关态电流分别为 0 .2 8V、 490 m S/m和 0 .0 8n A/μm ;而 PMOS阈值电压、跨导和关态电流分别为- 0 .3V、 34 0 m S/m m和 0 .2 n A /μm .并研制成功了 10 0 nm栅长的 CMOS 5 7级环形振荡器 ,其在 1.5 V、 2 V和 3V电源电压下的延迟分别为 2 3.5 ps/级、 17.5 ps/级和 12 .5

A high performance 70nm CMOS device has been demonstrated for the first time in the continent, China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, such as 3nm nitrided oxide, dual poly Si gate electrode, novel super steep retrograde channel doping by heavy ion implantation, ultra shallow S/D extension formed by Ge PAI(Pre Amorphism Implantation) plus LEI(Low Energy Implantation), thin and low resistance Ti SALICIDE by Ge PAI and special cleaning, etc. The shortest channel length of the CMOS device is 70nm. The threshold voltages, G m and off current are 0 28V,490mS·mm -1 and 0 08nA/μm for NMOS and -0 3V,340mS·mm -1 and 0 2nA/μm for PMOS, respectively. Delays of 23 5ps/stage at 1 5V, 17 5ps/stage at 2 0V and 12 5ps/stage at 3V are achieved in the 57 stage unloaded 100nm CMOS ring oscillator circuits.