基于FPGA的内插定时恢复算法的实现

Implementation of Interpolation Timing Recovery Algorithm Based on FPGA

提出了一种基于FPGA的内插定时恢复算法的实现方法,重点分析了算法中的内插滤波器、定时误差检测器、环路滤波器和控制器等模块的原理。通过用Simulink对算法进行仿真,从而了解并掌握模块的工作过程,且对这四个模块进行FPGA的设计,在QuartusⅡ 9.1平台上对内插法中的各模块的设计进行了仿真。

A method based on FPGA for implementing timing recover algorithm is presented. The principles of the interpolation filter, timing error detector, loop filter and controller are analyzed. Through simulations on the Simulink plantform, the work procedures of various modules are understood and mastered. The four modules are also designed on the FPGA plant- form. Simulations are conducted on the Quartus II 9.1 platform.