一种简易的总线传输协议

A Simple Bus Transfer Protocol

在片上系统(System on Chip,SoC)通信中,主机与从机进行通信时,为了实现主机与从机之间的高速寄存器读写操作,提出了一种由主机发起、从机响应、低位宽和高速率的总线传输协议。该总线由片选使能线、时钟传输线和双向数据传输线组成,分析了传输时主机写从机、主机读从机的总线行为,以及主机解析从机写操作和从机解析主机读操作的过程。采用VHDL语言实现了总线的硬件设计,并对总线的读写行为做了功能和性能测试,该总线接口可以满足实际应用需求。

In order to achieve the high-speed register read and write operations between master and slave of the on-chip system communication,we propose a low bit-width and high-speed bus transfer protocol which is initiated by the master and responded by the slave.The bus consists of a chip select enable line,a clock transmission line and a two-way data transmission line.We analyze the bus behavior when the master writes and reads the slave during transmission, as well as the process of the master analyzing the writing operation of the slave and the slave analyzing the reading operation of the master.The hardware design of the bus is implemented by using VHDL,and the functionality and performance test of the writing and reading behavior of the bus are done.The bus interface can meet the requirements of practical application.