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基于动态衬底电阻的自衬底触发ESD保护器件

A self-substrate-triggered ESD protection device based on dynamic substrate resistance
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摘要 利用版图设计方法对衬底触发多叉指GGNMOS器件进行了改进设计,优化了多叉指保护器件的触发均匀性。同时通过在保护器件源极扩散区周围增加N阱环来增大等效衬底电阻,以提高其触发性能。器件仿真结果表明,与传统GGNMOS器件和普通衬底触发GGNMOS器件相比,所提出的基于动态衬底电阻的自衬底触发GGNMOS结构的ESD鲁棒性达到了9.7 mA/μm,同时触发电压也降低了约32%,达到了提高保护器件ESD鲁棒性和降低触发电压的目的。 The design of substrate triggered multifinger GGNMOS is improved using the layout design method, which optimizes the trigger uniformity of the protection device. Meanwhile, the trigger performance is improved by adding N-well ring around the source diffusion of the protection device. The device simulation result shows that the ESD robustness of the new self substrate triggered GGNMOS based on dynamic substrate resistance is improved to 9.7mA/txm and the trigger voltage is also reduced by 32%.
作者 吴晓鹏 杨银堂 董刚
机构地区 西安电子科技大学微电子学院/宽禁带半导体材料与器件教育部重点实验室
出处 《西北大学学报（自然科学版）》 CAS CSCD 北大核心 2014年第1期41-45,共5页 Journal of Northwest University（Natural Science Edition）
基金 国防预研究基金资助项目(9140A23060111) 陕西省科技统筹创新工程计划基金资助项目(2011KTCQ01-19) 中央高校基本科研业务费专项基金资助项目(2013-01)
关键词 静电放电 多叉指GGNMOS 自衬底触发 动态衬底电阻 electrostatic discharge muhifinger GGNMOS self substrate trigger dynamic substrate resistance
分类号 TN386 [电子电信—物理电子学]
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参考文献12

  • 1YEH C T,KER M D. Resistor-less design of powerrail ESD clamp circuit in nanoscale CMOS technology[J].{H}IEEE Transactions on Electron Devices,2012,(12):3456-3463.
  • 2WONJI,JUNGJW,YANGIS. Design of ESD protection device using body floating technique in 65nm CMOS process[J].{H}Electronics Letters,2011,(19):1072-1073.
  • 3DUVVURY C,BOSELLI G. ESD and latch-up reliability for nanometer CMOS technologies[A].San Francisco:IEEE,2004.933-936.
  • 4KWANG-HOON Oh,DUVVURY C,BANERJEE K. Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors[J].{H}IEEE Transactions on Electron Devices,2002,(12):2171-2182.
  • 5VASHCHENKO V A,CONCANNON A,TER BEEK M. Physical limitation of the cascaded snapback NMOS ESD protection capability due to the non-uniform turn-off[J].{H}IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY,2004,(02):281-291.
  • 6WANG Y,JIA S,CHEN Z J. A design model of gate-coupling NMOS ESD protection circuit[A].Beijing:IEEE,2004.1637-1640.
  • 7YONG-SEO K,KWI-DONG K,JONG-KEE K. ESD protection circuit with low triggering voltage and fast turn-on using substrate-triggered technique[J].{H}IEICE ELECTRONICS EXPRESS,2009,(08):467-471.
  • 8KER M D,CHEN J H. Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices[J].{H}IEEE Journal of Solid-State Circuits,2006,(11):2601-2609.doi:10.1109/JSSC.2006.883331.
  • 9CHATTY K,ALVAREZ D,GAUTHIER R. Process and design optimization of a protection scheme based on NMOSFETs with ESD Implant in 65nm and 45nm CMOS technologies[A].Anaheim:IEEE,2007.7A.2-1-7A.2-10.
  • 10KER M D,CHEN T Y. Substrate-triggered technique for on-chip ESD protection design in a 0.18-μm salicided CMOS process[J].{H}IEEE Transactions on Electron Devices,2003,(04):1050-1057.
西北大学学报（自然科学版）
2014年 第1期

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