一种模拟除法器的设计

Design of a Analogue Divider

设计了一种模拟除法器,核心电路由第二代电流传输器和一个电压电流转换电路构成。采用CSMC0.5umCMOS工艺进行设计,并用Cadence Spectre软件对电路进行了仿真,结果表明,在+5V的单电源供电下,-3dB带宽达到了60MHz,整个电路的静态功耗低至4.5mW。

A analogue divider is presented in this paper, which consists of the second generation current conveyor and the vol- tage-to-current converter. The results which is simulated with the Cadence Spectre based on CSMC 0.5um CMOS process shows that ,under ＋5V supply voltages, the -3dB bandwidth is about 60MHz, and the power dissipation is less than 4.5mW.