一种嵌入式MPU指令译码器设计

Design of Instruction Decoder for Use in China for an Embedded MPU

针对与 Intel系列微处理器兼容的嵌入式微处理器单元 (MPU) ,讨论其译码器的设计问题。通过分析比较两种可行的读入方案 ,择优选用了在状态机控制下的指令读入机制 ,并设计了具有 8个状态的状态机来控制指令读入 ,实现了复杂指令简单化的目的。采用表格技术将译码器与微程序的设计分离。译码器位于 MPU指令流水线的中部 ,其输出队列的长度影响 MPU的性能 ,文中近似采用 M/ M/ 1 / K排队系统的分析方法 ,确定了输出队列长度。译码器与 MPU的其它部分联调完成后 ,使用具有实际意义的应用程序进行测试的结果表明 ,该译码器的设计是合理有效的。

In accordance with an embedded microprocessor unit (MPU) which is compatible with Intel series microprocessor at instruction (eve), the design of the instruction decoder was discussed. The structure of the complex instruction set was analyzed and classified. After two kinds of feasible input schemes were compared, the instruction input mechanism under the control of state machine was selected. An eight-state state machine was designed to implement simplification for the complex instruction. The table technique was used to generate entry addresses of microprogram, so was to implement design separation for decoder and microprogram. The decoder was located in the middle of MPU's instruction pipeline, and the length of output queue influences the performance of MPU. The M/M/L/K model was used to analyze the queue system and determine the queue length. Test result has been shown that the design of the decoder is reasonable and effective.