摘要
设计了一种应用于DRFM系统的4bit相位量化DAC,采用非线性的电流舵结构在标准半导体工艺下实现,芯片面积2.1mm×1.4mm,功耗420mW。测试结果显示该DAC瞬时带宽高于1GHz,与4bit相位量化ADC级联测试时,SFDR在工作带宽内小于-20dBc,性能明显优于3bit相位量化DAC。
A 4 bit phase digitizing DAC for DRFM with the area of 2.1 minx 1.4 mm and the power consumption of 420 mW was designed by adopting the nonlinear current steering structure and implemented by standard semiconductor technology. Test results show that the instantaneous bandwidth of DAC is higher than 1 GHz. When it is cascade-connected with the 4 bit phase digiti- zing ADC,the measured SFDR is better than -20 dBc. The performance of this 4 bit phase DAC is superior to the 3 bit one.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2014年第1期24-28,共5页
Research & Progress of SSE
关键词
数模转换器
相位量化
数字射频存储器
电流舵
无杂散噪声动态范围
digital-to-analog converter（DAC）
phase digitizing
digital radio frequency memory（DRFM）
current steering
spurious-noise-free dynamic range（SFDR）
