基于AMBA总线的IIC协议IP核设计与验证

Design and Verification of IP Core of IIC Protocol Based on AMBA Bus

介绍了一种基于AMBA总线verilog HDL实现的IIC主机模式的IP核设计。该模块能够在标准和快速模式下运行,能够灵活配置为十位地址寻址或七位地址寻址模式。详细说明了该IP核的架构,各部分设计及状态转换过程。最后该模块通过了系统验证,并在xilinx FPGA上转化为硬件电路实现了所有功能。

This article describes an IP core design of IIC master, base on AMBA bus, which implements by verilog HDL. The module can runs in standard mode and quick mode, and it can be flexibly configured to be ten bit or seven bit addressing mode. This article describes the structure of IP core, and its design and status conversion process. Finally, the module has passed the system -level verification and all functions have been implemented in Xilinx FPGA hardware.