基于FPGA的加密算法改进及实现

Improvement and Implementation of Encryption Algorithm Based on FPGA

以FPGA芯片Cyclone II系列为核心,构建FPGA硬件平台,提出一种以资源优先为目的的DES、AES加解密设计方案。通过分析S盒的非线性特征,构造新的复合域变换,避免因同构变换产生的资源损耗。加解密过程中利用轮函数硬件结构的复用,达到硬件资源占用的最小化。整体采用内嵌流水线结构,减少逻辑复杂度的同时提高处理速度。实验结果验证了FPGA硬件加密的资源占用率远低于ASIC的硬件加密,执行速度达到Gbit/s,加密性能大大提高。

A design of high performance hardware encryption system with Advanced Encryption Standard （AES） and Data Encryption Standard （DES） implementations based on FPGA is described in this paper. Verilog HDL modules are synthesized on Cyclone II FPGA platform. By analyzing the nonlin-ear characteristics of S-box, a new composite field transformation is introduced which avoids waste of hardware resources. The advantage of round func- tion hardware multiplexing in the encryption and decryption procedure is that it minimizes the occupied hardware resource. The pipelined architecture used in this work reduces the logic complexity with greater flexibility and hardware efficiency. The results show that the resource of hardware encryption used in FPGA is far less than in ASIC and a higher throughput of Gbit/s is achieved.