可编程Viterbi译码器设计与实现

Design and implementation for programmable Viterbi decoder

卷积编码作为一种优秀的信道编码方式,已被广泛应用在卫星通信和无线通信系统中。在它所对应的译码方式中,Viterbi译码性能较优。Viterbi译码是一种最大似然译码算法,不仅译码速度快,而且其硬件实现简单。提出了一种专用指令集处理器架构,能够支持多种约束长度的Viterbi译码,为通信系统在信道编解码方面做出了有益的尝试。设计了专用的处理器架构,并对(2,1,7)格式的编码进行了ASIC实现,对两种设计的性能进行了对比,可编程Viterbi译码器的最大工作频率为123 MHz。

As an excellent way of channel coding,convolution encoding is used in the satellite communication and wireless communication system.In contrast to other decoding method,the performance of Viterbi decoding is better.It is a kind of maximum likelihood decoding algorithm,whose decode performance is good and fast,with simple hardware implementation circuit.This paper proposes a specific instruction set processor architecture,is able to support multiple constraint length of Viterbi decoding,has made the beneficial attempt for the communication system in terms of channel transmission.The dedicated processor architecture is designed and the coding of （2,1,7） format is implemented by ASIC.Compared the performance of the two design,the maximum working frequency of the programmable Viterbi decoder is 123 MHz.