摘要
为了提高DLMS自适应滤波器的处理速度、降低其FPGA实现时所消耗的逻辑资源,提出了一种特殊DA方案。此方案基本结构主要包含I-LUT和K-LUT两个模块,前者用于存放输入采样值的所有可能组合之和,后者用于更新该滤波器的权值并且计算其输出信号。Matlab软件仿真验证了该自适应滤波器设计的可行性和正确性,Quartus II硬件仿真证明,基于此DA方案的自适应滤波器比基于通常的MAC方案的自适应滤波器具有更高的处理速度且消耗更少的逻辑资源。
A special DA scheme is proposed to increase the processing speed of the DLMS adaptive filter and decrease the consumption of logic elements of FPGA.The basic structure of this scheme mainly contains Ⅰ-LUT and K-LUT modules.The former is used to store all possible combination sums of the input samples,the latter is utilized to update the adaptive filter＇s weights and compute its output signal.Matlab software simulation proves the feasibility and correctness of the design of adaptive filter.Quartus Ⅱ hardware simulation verifies that the adaptive filter based on the DA scheme has higher processing speed and consumes less logic elements.
出处
《电子技术应用》
北大核心
2014年第3期35-37,40,共4页
Application of Electronic Technique
基金
国家自然科学基金(11204109)
关键词
自适应滤波器
分布式算法
延迟最小均方
查找表
FPGA
adaptive filter
distributed arithmetic（DA）
delay least mean square（DLMS）
look up table（LUT）
FPGA
