一种可重构数据压缩信息处理系统的设计实现

Design and Realization of Reconfigurable Data Compression System

本文介绍可重构电子系统相关技术的发展现状,在分析了JPEG2000标准编解码芯片ADV212内部结构和工作原理的基础上,提出了一种可重构的数据压缩信息处理系统设计方案,它结合了FPGA器件的灵活性和专用图像数据编解码芯片的高效性,系统架构上主要运用FPGA资源实现系统重构,即运用可编程逻辑对图像数据压缩芯片ADV212进行寄存器配置、数据码流调度控制以及系统时序逻辑适配。经过图像数据的压缩解压对比测试,该数据压缩信息处理系统具有较高的峰值信噪比(PSNR),在实现了系统可重构同时,能够满足某型高速光通信系统对图像数据压缩实时性和数据完整性的要求。

This paper introduces the development status of reconfigurable electronic systems technology-, after ,analyzing on ADV212, a JPEG2000 standard codec ASIC, proposed a design scheme of an reconfigurable image data compression system, it combines the flexibility, of FPGA devices and the efficiency of AS1C, it used FPGA resources on system reconfiguration.Tests and experimental results show that the reconfigdrable imagc compression system with higher peak signal to noise ratio（PSNR）, it is able to meet a communication system＇ s requirement on real time and data integrity of image compression.