摘要
提出了一种基于ISO/IEC15693协议的标签芯片编解码系统设计的实现方法,使编解码更加完整准确。采用Verilog HDL建立RTL模型,用ModelSim进行功能仿真,并在Altera DE2-115与射频前端搭建的平台上进行了FPGA验证。最后不仅功能验证正确,而且比协议中要求的识别凹槽宽度范围广,处理更加灵活,同时减小了射频前端模拟解调的压力。对其他编解码系统的实现也有一定的借鉴意义。
A method was designed for achieving codec about tag chip according to ISO/IEC15693 protocol,which made codec more complete and accurate. Verilog HDL was used to created RTL models, functional simulation was carried out with ModelSim and FPGA was validated on Altera DE2-115 and RF front-end platform.Finally, not only the function was verified correct,but also the identification scope of pause width is wide, the process is more flexible.At the same time,the pressure of the RF front-end analog demodulation was reduced. It also has a certain significance to other codec implementations.
出处
《电子技术应用》
北大核心
2014年第2期36-38,共3页
Application of Electronic Technique
基金
交通运输部科技项目(2011-364-813-060)
