2.45GHz 0.18μm CMOS高线性功率放大器设计

Design of a 2.45 GHz 0.18 μm CMOS highly linear power amplifier

为了在更高的电源电压下工作,并便于匹配网络的设计,电路采用两级共源共栅架构。采用自偏置技术放宽功放的热载流子降低的限制并减小采用厚栅晶体管所带来的较差的射频性能。同时使用带隙基准产生一个稳定且独立于工艺和温度变化的直流基准。采用SMIC 0.18μm RF CMOS工艺进行设计,该功率放大器的中心工作频率为2.45 GHz,并利用Cadence公司的spectreRF进行仿真。仿真结果显示,在3.3 V工作电压下,最大输出功率为30.68 dBm,1 dB压缩点处输出功率为28.21 dBm,功率附加效率PAE为30.26%。所设计的版图面积为1.5 mm×1 mm。

Two-stage cascode structure is applied for higher maximum supply voltage and ease of matching network design. A self-biasing technique is presented that relaxes the restriction due to hot carrier degradation in power amplifiers and alleviates the need to use thick-oxide transistors that have poor RF performance. A bandgap reference is used to provide a stable DC reference which is immune to the process and temperature variations. The PA is fabricated in an SMIC 0.18 μm RF CMOS process technolo- gy, the working frequency of this power amplifier is 2.45 GHz. It is simulated with Cadence spectreRF. According to the simulation results, under 3.3 V supply voltage, the saturated output power of the designed PA reaches to 30.68 dBm and output power reach- es to 28.21 dBm with a power-added efficiency（PAE） of 30.26% at 1 dB compression point. The layout size is 1.5 mm×1 mm.