摘要
针对60 GHz无线个域网,提出了一种平衡加选延比式维特比译码架构,打破了原有维特比译码器的速率瓶颈。基于该推荐架构,实现了一种8路并行基-2(3,1,7)维特比译码器。在TSMC.13CMOS工艺下,该译码器以0.104 nJ/bit和4.33 mm2的能耗资源花销,实现了高达4 Gb/s的吞吐率。
In this paper, a novel balanced add-select-delay-compare Viterbi decoding architecture is proposed for the 60 GHz wireless personal-area network, which breaks the bottleneck of decoding speed in traditional Viterbi decoders. According to the pro- posed architecture, this paper designs a parallel-8 radix-2 （3,1,7） Viterbi decoder. In TSMC.13 CMOS technology, the decoder achieves up to 4 Gb/s throughput with the cost of 0.104 nJ/bit and 4.33 mm2.
出处
《电子技术应用》
北大核心
2014年第2期94-96,100,共4页
Application of Electronic Technique
关键词
维特比译码器
60
GHz无线个域网
平衡加选延比式
高吞吐率
viterbi decoder
60 GHz wireless personal-area network
balanced add-select-delay-compare architecture
highthroughput
