摘要
在飞行模拟器的设计中,为了使数据能够快速有效地在飞行模拟器的各个模块之间进行高速传递,提出了一种使用FPGA作为CAN总线节点结构中的核心处理器的设计方法,并完成了飞行模拟器通信接口的软硬件设计。采用Verilog HDL进行编程,能够完成对SJA1000总线控制器的有效读写。实际测试表明,相较于单片机作为处理器,本设计可扩展性好,易于修改和移植,能降低模拟器成本。
In the design of the flight simulator,in order to have the data conveyed quickly and efficiently among every model of the flight simulator,the new design come up with a method using FPGA as the processor of CAN bus and finish the hardware and software's design of flight simulator's interface communication.The software system adopts the Verilog HDL to program.The system can accomplish the reading and writing efficiently to controller of SJA1000 CAN bus.Comparing to using the MCU as processor,the experiment shows that this design which is expendability can be changed and easy-to-port and cut down the cost of the simulator.
出处
《电子设计工程》
2014年第3期88-90,共3页
Electronic Design Engineering