运动估计芯片的缓存设计策略及FPGA验证

The Design Scheme of Motion Estimation Chip's Cache Architecture and It's Simulation Using FPGA

为解决更高视频图像中向运动估计芯片供数的存储器带宽过高的问题 ,提出了局存容量的设计策略。通过分析块匹配运动估计模型的特征和VLSI的要求 ,给出评价运动估计芯片局存的两个指标 ,由此得到一个制定局存容量的策略。遵照这一策略 ,为运动估计芯片提供了几个工程可用的指标。该研究来自于实现运动估计芯片的工作 ,对研究MPEG 2视频编码器的VLIS实时实现有一定的参考价值。

A design scheme of cache's capability is proposed. Firstly, two quotas which are used for evaluating ME's cache are given according to the character of the block match mode and VLSI, then an scheme of laying down the capability of cache is obtained. According to this scheme, several engineering parameters are proposed. Because the research comes from the work of ME chip's realization, it is beneficial to the work of researching MPEG 2' encoder.