基于FPGA的交流伺服系统电流环带宽扩展

Bandwidth expansion of current loop for AC servo system based on FPGA

在电流环的数学模型基础上,分析了电流环带宽与电流环路延时的关系,比较了几种典型电流环时序下产生的延时,对电流采样和PWM占空比更新时序进行了改进,并在FPGA中得到了具体的验证和实现.实验结果表明:这种改进的电流环时序克服了原有电流环时序的问题,能在不改变功率器件开关频率和不损失输出电压能力的基础上减小电流环路延时,从而提高电流环带宽,改善电流环和速度环的控制性能.

The relationship between current loop bandwidth and time delay were analyzed based on a mathematical model of the current loop and the time delay generated by several typical current loop timings was compared .The timing of current sampling and PWM duty update was improved ,which was verified and implemented on one-chip FPGA （field-programmable gate array ） .Experimental re-sults show that the improved current loop timing can reduce the current loop delay to increase the cur-rent loop bandwidth without changing the switching frequency and losing output voltage capability . Therefore ,the control performances of current loop and speed loop were improved .