Optimal Stack Generation for CMOS Analog Modules with Parasitic and Mismatch Constraints

带寄生及匹配约束的 CMOS模拟电路模块的 STACK生成优化方法(英文)

The performances of analog circuits depend greatly on the layout parasitics and mismatches.Novel techniques are proposed for modeling the distributed parasitic capacitance,parasitic parameter mismatch due to process gradient and the inner stack routing mismatch.Based on the proposed models,an optimal stack generation technique is developed to control the parasitics and mismatches,optimize the stack shape and ensure the generation of an Eulerian graph for a given CMOS analog module.An OPA circuit example is given to demonstrate that the circuit performances such as unit gain bandwidth and phase margin are enhanced by the proposed layout optimization method.

模拟电路的性能紧密依赖于版图的寄生参数和匹配特性 .提出了用以描述分布式的寄生电容和由于工艺梯度变化而产生的寄生参数不匹配以及 STACK内连线的不匹配的模型 .基于该模型 ,一种新的 STACK生成方法用来控制版图的寄生参数和匹配特性 ,优化 STACK的形状和确保为所给出的模拟电路模块生成相映的欧拉图 .一个