CMOS/SOI64Kb静态随机存储器

Developmentof CMOS/ SOI64Kb SRAM

对一种 CMOS/ SOI6 4Kb静态随机存储器进行了研究 ,其电路采用 8K× 8的并行结构体系 .为了提高电路的速度 ,采用地址转换监控 ( Address- Translate- Detector,ATD)、两级字线 ( Double- Word- L ine,DWL)和新型的两级灵敏放大等技术 ,电路存取时间仅 40 ns;同时 ,重点研究了 SOI静电泄放 ( Electrostatic- Discharge,ESD)保护电路和一种改进的灵敏放大器 ,设计出一套全新 ESD电路 ,其抗静电能力高达 42 0 0— 45 0 0 V.SOI6 4KbCMOS静态存储器采用 1.2 μm SOI CMOS抗辐照工艺技术 ,芯片尺寸为 7.8m m× 7.2

An SOI SRAM with 8K× 8concurrentsystem has been described. To reduce the power and raise the speed of cir- cuit,addess- transition- detection,doubl- word- line and double double- stage sense amplifier technology,etc. are adopted. Fast access time of 40 ns is abtained. Placing great emphasis on the investigation of SOI ESD ( Electrostatic- Discharge) protection circuit and the im proved am plifier,a set of optim um ESD circuit is designed,which is capable of protecting from the static dis- charge in excess of 42 0 0— 45 0 0 V. 1.2μm SOI CMOS technology has been developed for SOI 6 4Kb CMOS SRAM,with the chip size of 7.8m m× 7.2 4mm .