基于FPGA的面阵CCD驱动时序设计

The design of drive timing generation of array CCD based on FPGA

针对柯达公司的前照明行间转移型面阵CCD KAI-0340,对它的驱动时序进行详细的分析,设计满足CCD工作脉冲的驱动时序。采用Altera公司的可编程逻辑器件(FPGA)作为核心控制器件,完成自顶而下的模块设计,实现了硬件电路设计的软件化,开发效率得到了提高,软件程序可重复编程和修改。实验的仿真结果表明,设计的驱动时序能够满足CCD KAI-0340的正常工作。

A detailed analysis was carried out of the requirements of the driving timing sequence of the progressive scan interline CCD KAI-0340 produced by Kodak Company.The programmable logic device （FPGA） of Altera Company was used for designing CCD driving timing sequence,which could enable the use of software in the designing of hardware circuit and improve development efficiency because the software was reprogrammable and modifiable.Results of experimental simulation showed that the designed sequence could meet the demand of the CCD KAI-0340.